AssertCraft generates SystemVerilog assertions from specification documents using subtask decomposition, fine-tuned GPT-3.5, and iterative compiler-guided repair, reporting 7.3x more correct assertions than a plain prompt baseline.
(security) assertions by large language models,
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Automatic High-quality Verilog Assertion Generation through Subtask-Focused Fine-Tuned LLMs and Iterative Prompting
AssertCraft generates SystemVerilog assertions from specification documents using subtask decomposition, fine-tuned GPT-3.5, and iterative compiler-guided repair, reporting 7.3x more correct assertions than a plain prompt baseline.