Fusing an ASIC mapper with a reinforcement-learning-chosen partial cell library improves FPGA LUT count and area-delay product by about 9% on average.
DRiLLS: Deep Reinforcement Learning for Logic Synthesis
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abstract
Logic synthesis requires extensive tuning of the synthesis optimization flow where the quality of results (QoR) depends on the sequence of optimizations used. Efficient design space exploration is challenging due to the exponential number of possible optimization permutations. Therefore, automating the optimization process is necessary. In this work, we propose a novel reinforcement learning-based methodology that navigates the optimization space without human intervention. We demonstrate the training of an Advantage Actor Critic (A2C) agent that seeks to minimize area subject to a timing constraint. Using the proposed methodology, designs can be optimized autonomously with no-humans in-loop. Evaluation on the comprehensive EPFL benchmark suite shows that the agent outperforms existing exploration methodologies and improves QoRs by an average of 13%.
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Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper
Fusing an ASIC mapper with a reinforcement-learning-chosen partial cell library improves FPGA LUT count and area-delay product by about 9% on average.