A Fourier-engineered cos(2φ) qubit achieves spectral agreement with theory but its energy relaxation is limited by 1/f flux noise from residual first-harmonic fluctuations, unlike similar fluxonium qubits.
Title resolution pending
4 Pith papers cite this work. Polarity classification is still indexing.
fields
quant-ph 4years
2026 4representative citing papers
Lighter fluxonium qubits show lower susceptibility to measurement-induced state transitions than heavier counterparts due to reduced multi-photon resonance density, smaller required coupling, and more harmonic charge operator structure.
A floating tunable coupler allows 24 ns adiabatic CZ gates above 99.9% fidelity with exact ZZ=0 at idle for fixed-frequency transmons.
A system-level design methodology for scalable fluxonium processors with double-transmon couplers that supports high-fidelity gates, fast reset, and dispersive readout through frequency partitioning under realistic constraints.
citing papers explorer
-
Coherence limitations of a Fourier-engineered $\cos(2\varphi)$ transmon qubit
A Fourier-engineered cos(2φ) qubit achieves spectral agreement with theory but its energy relaxation is limited by 1/f flux noise from residual first-harmonic fluctuations, unlike similar fluxonium qubits.
-
Measurement-induced state transitions across the fluxonium qubit landscape
Lighter fluxonium qubits show lower susceptibility to measurement-induced state transitions than heavier counterparts due to reduced multi-photon resonance density, smaller required coupling, and more harmonic charge operator structure.
-
Unlocking a fast adiabatic CZ gate and exact residual $ZZ$ cancellation between fixed-frequency transmons using a floating tunable coupler
A floating tunable coupler allows 24 ns adiabatic CZ gates above 99.9% fidelity with exact ZZ=0 at idle for fixed-frequency transmons.
-
System-Level Design of Scalable Fluxonium Quantum Processors with Double-Transmon Couplers
A system-level design methodology for scalable fluxonium processors with double-transmon couplers that supports high-fidelity gates, fast reset, and dispersive readout through frequency partitioning under realistic constraints.