Duet is a manycore-eFPGA architecture with cache-coherent integration that supports fine-grained acceleration and hardware augmentation, shown in RTL evaluation to cut communication latency by up to 82% and deliver 1.5-24.9x speedups on seven benchmarks.
FracBNN: Accurate and FPGA-efficient binary neural networks with fractional ac- tivations
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A co-design framework using approximate matrix decomposition and genetic algorithms delivers 33% average latency reduction in TinyML CNN FPGA accelerators with 1.3% average accuracy loss versus standard systolic arrays.
citing papers explorer
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Duet: Creating Harmony between Processors and Embedded FPGAs
Duet is a manycore-eFPGA architecture with cache-coherent integration that supports fine-grained acceleration and hardware augmentation, shown in RTL evaluation to cut communication latency by up to 82% and deliver 1.5-24.9x speedups on seven benchmarks.
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Co-Design of CNN Accelerators for TinyML using Approximate Matrix Decomposition
A co-design framework using approximate matrix decomposition and genetic algorithms delivers 33% average latency reduction in TinyML CNN FPGA accelerators with 1.3% average accuracy loss versus standard systolic arrays.