Arch is a new AI-native HDL that uses parameterized clock/reset types and built-in hardware primitives to enable type-safe, AI-generatable register-transfer designs compiling to SystemVerilog with automatic formal properties.
https://circt.llvm.org/, 2024
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Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design
Arch is a new AI-native HDL that uses parameterized clock/reset types and built-in hardware primitives to enable type-safe, AI-generatable register-transfer designs compiling to SystemVerilog with automatic formal properties.