On the same SoC and 22nm technology, a RISC-V-compliant out-of-order core matches the energy efficiency of in-order cores above 500 MHz, while an enhanced dual-issue core is most area-efficient.
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Ramping Up Open-Source RISC-V Cores: Assessing the Energy Efficiency of Superscalar, Out-of-Order Execution
On the same SoC and 22nm technology, a RISC-V-compliant out-of-order core matches the energy efficiency of in-order cores above 500 MHz, while an enhanced dual-issue core is most area-efficient.