SPARK is a sparsity-aware near-cache ILP accelerator achieving up to 15x performance and 152x energy reduction over CPUs for sparse ILPs on MIPLIB 2017 workloads.
Ising-cim: A reconfigurable and scalable compute within memory ana- log ising accelerator for solving combinatorial optimization problems,
2 Pith papers cite this work. Polarity classification is still indexing.
2
Pith papers citing it
fields
cs.AR 2years
2026 2verdicts
UNVERDICTED 2representative citing papers
SACHI reuses CPU L1 cache for all-digital Ising acceleration and reports 300x performance and 80x energy gains over BRIM on asset allocation, molecular dynamics, image segmentation, and TSP.
citing papers explorer
-
A comprehensive study on ILP acceleration accounting for sparsity, area, energy, data movement using near-memory architecture
SPARK is a sparsity-aware near-cache ILP accelerator achieving up to 15x performance and 152x energy reduction over CPUs for sparse ILPs on MIPLIB 2017 workloads.
-
A detailed algorithmic study on a reuse-aware, near memory, all-digital Ising machine
SACHI reuses CPU L1 cache for all-digital Ising acceleration and reports 300x performance and 80x energy gains over BRIM on asset allocation, molecular dynamics, image segmentation, and TSP.