This is the first reported FPGA implementation of the L-Mul approximate multiplier for FP8, using about 22 lookup tables per multiplier and showing lower power in CNN/GCN inference.
Extremely low-bit convolution optimization for quantized neural network on modern computer architec- tures,
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A Power-Efficient Hardware Implementation of L-Mul
This is the first reported FPGA implementation of the L-Mul approximate multiplier for FP8, using about 22 lookup tables per multiplier and showing lower power in CNN/GCN inference.