A new in-situ scheme prepares logical magic states inside arbitrary CSS qLDPC codes using only syndrome-extraction ancillas, with simulations on the [[144,12,12]] BB code and [[225,9,4]] hypergraph-product code showing injection error rates around 10^{-3} or lower under depolarizing and asymmetric噪声
Fast and parallelizable logical computation with homological product codes
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A 256-atom neutral ytterbium processor demonstrates fault-tolerant entanglement of 24 logical qubits and runs Bernstein-Vazirani on 28 logical qubits with better-than-physical error rates using erasure conversion.
A hot-zone architecture for OQFT on reconfigurable neutral-atom hardware yields tunable latency via 2-4 zones, converging to roughly 500 extra logical ancillae and 128-qubit peak parallelism for half-time performance on 256-2048 bit instances.
CAbLECAR provides a robotics-inspired shuttle scheduler that enables QLDPC codes on tileable spin-qubit hardware, yielding up to 86% faster schedules and orders-of-magnitude gains in encoding efficiency and logical error rates over surface codes.
Shor's algorithm for cryptographically relevant problems becomes feasible on neutral-atom systems with as few as 10,000 reconfigurable physical qubits via high-rate quantum error correction.
The paper identifies four key hurdles in the transition from NISQ to FASQ quantum computers and argues that targeting them will accelerate progress toward useful quantum advantage.
citing papers explorer
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In-Situ Simultaneous Magic State Injection on Arbitrary CSS qLDPC Codes
A new in-situ scheme prepares logical magic states inside arbitrary CSS qLDPC codes using only syndrome-extraction ancillas, with simulations on the [[144,12,12]] BB code and [[225,9,4]] hypergraph-product code showing injection error rates around 10^{-3} or lower under depolarizing and asymmetric噪声
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Fault-tolerant quantum computation with a neutral atom processor
A 256-atom neutral ytterbium processor demonstrates fault-tolerant entanglement of 24 logical qubits and runs Bernstein-Vazirani on 28 logical qubits with better-than-physical error rates using erasure conversion.
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Towards Deploying Optimistic Quantum Fourier Transforms: An Architecture-Algorithm Co-Design Study
A hot-zone architecture for OQFT on reconfigurable neutral-atom hardware yields tunable latency via 2-4 zones, converging to roughly 500 extra logical ancillae and 128-qubit peak parallelism for half-time performance on 256-2048 bit instances.
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CAbLECAR: efficiently scheduling QLDPC codes on a tileable spin qubit chip with shuttling
CAbLECAR provides a robotics-inspired shuttle scheduler that enables QLDPC codes on tileable spin-qubit hardware, yielding up to 86% faster schedules and orders-of-magnitude gains in encoding efficiency and logical error rates over surface codes.
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Shor's algorithm is possible with as few as 10,000 reconfigurable atomic qubits
Shor's algorithm for cryptographically relevant problems becomes feasible on neutral-atom systems with as few as 10,000 reconfigurable physical qubits via high-rate quantum error correction.
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Mind the gaps: The fraught road to quantum advantage
The paper identifies four key hurdles in the transition from NISQ to FASQ quantum computers and argues that targeting them will accelerate progress toward useful quantum advantage.