Introduces a quality-aware loop with mutation-guided refinement, RTL-aware solver selection, and causal narrative synthesis to improve LLM-generated assertions for formal verification of RTL designs.
Specllm: Exploring generation and review of VLSI design specification with large language model,
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Closing the Loop on LLM-Generated RTL Assertions with Quality-Aware Formal Verification
Introduces a quality-aware loop with mutation-guided refinement, RTL-aware solver selection, and causal narrative synthesis to improve LLM-generated assertions for formal verification of RTL designs.