A new Verilog vectorizer on CIRCT yields 28% faster elaboration and 51% lower memory use for the Jasper formal verification tool across 1,157 ChiBench designs.
Lazy evaluation for the lazy: Automatically transforming call-by-value into call-by-need
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Vectorization of Verilog Designs and its Effects on Verification and Synthesis
A new Verilog vectorizer on CIRCT yields 28% faster elaboration and 51% lower memory use for the Jasper formal verification tool across 1,157 ChiBench designs.