Duet is a manycore-eFPGA architecture with cache-coherent integration that supports fine-grained acceleration and hardware augmentation, shown in RTL evaluation to cut communication latency by up to 82% and deliver 1.5-24.9x speedups on seven benchmarks.
Decoupled Access/Execute Computer Architectures,
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DAE4HLS enables explicit decoupling of access and execute in HLS to unlock memory-level parallelism, delivering 10-79x speedups for complex workloads on commercial and dynamic HLS tools.
citing papers explorer
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Duet: Creating Harmony between Processors and Embedded FPGAs
Duet is a manycore-eFPGA architecture with cache-coherent integration that supports fine-grained acceleration and hardware augmentation, shown in RTL evaluation to cut communication latency by up to 82% and deliver 1.5-24.9x speedups on seven benchmarks.
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DAE4HLS: Exposing Memory-Level Parallelism for High-Level Synthesis using Explicit Decoupling
DAE4HLS enables explicit decoupling of access and execute in HLS to unlock memory-level parallelism, delivering 10-79x speedups for complex workloads on commercial and dynamic HLS tools.