Multiple double matrix multiplication on FP64 tensor cores is achieved by splitting doubles into 13-bit quarters with trailing zeros, enabling error-free inner products without branching renormalization.
Title resolution pending
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.MS 1years
2026 1verdicts
CONDITIONAL 1representative citing papers
citing papers explorer
-
Multiple Double Arithmetic on NVIDIA Tensor Cores
Multiple double matrix multiplication on FP64 tensor cores is achieved by splitting doubles into 13-bit quarters with trailing zeros, enabling error-free inner products without branching renormalization.