The paper reports a working implementation of the RISC-V H hypervisor extension in gem5, validated by booting Xvisor with guest Linux and by running nine MiBench workloads with and without a VM.
A First Look at RISC-V Virtualization from an Embedded Systems Perspective
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abstract
This article describes the first public implementation and evaluation of the latest version of the RISC-V hypervisor extension (H-extension v0.6.1) specification in a Rocket chip core. To perform a meaningful evaluation for modern multi-core embedded and mixedcriticality systems, we have ported Bao, an open-source static partitioning hypervisor, to RISC-V. We have also extended the RISC-V platformlevel interrupt controller (PLIC) to enable direct guest interrupt injection with low and deterministic latency and we have enhanced the timer infrastructure to avoid trap and emulation overheads. Experiments were carried out in FireSim, a cycle-accurate, FPGA-accelerated simulator, and the system was also successfully deployed and tested in a Zynq UltraScale+ MPSoC ZCU104. Our hardware implementation was opensourced and is currently in use by the RISC-V community towards the ratification of the H-extension specification.
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Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension
The paper reports a working implementation of the RISC-V H hypervisor extension in gem5, validated by booting Xvisor with guest Linux and by running nine MiBench workloads with and without a VM.