A new dataset of VHDL, Chisel, and PyMTL3 code paired with compiled Verilog improves LLM Verilog generation by up to 23% on VerilogEvalV2 after fine-tuning.
Available: https://repositorystats.com/
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
citation-role summary
background 1
citation-polarity summary
fields
cs.AR 1years
2025 1verdicts
CONDITIONAL 1roles
background 1polarities
support 1representative citing papers
citing papers explorer
-
hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation
A new dataset of VHDL, Chisel, and PyMTL3 code paired with compiled Verilog improves LLM Verilog generation by up to 23% on VerilogEvalV2 after fine-tuning.