A workload-aware surface-code architecture with ancilla-centric patches and T-gate-based floorplanning reduces required data tiles by up to 21% while maintaining near-optimal cycles per instruction and reaching 90% efficiency for 10 concurrent programs.
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Toward designing workload-aware Surface Code Architectures
A workload-aware surface-code architecture with ancilla-centric patches and T-gate-based floorplanning reduces required data tiles by up to 21% while maintaining near-optimal cycles per instruction and reaching 90% efficiency for 10 concurrent programs.