New merge booster and diagonal detector components, combined with cache blocking and gate fusion, deliver up to 160x speedup on circuit benchmarks and 34x on diagonal-heavy gates versus prior simulators.
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Large-Scale Quantum Circuit Simulation on HPC Cluster via Cache Blocking, Boosting, and Gate Fusion Optimization
New merge booster and diagonal detector components, combined with cache blocking and gate fusion, deliver up to 160x speedup on circuit benchmarks and 34x on diagonal-heavy gates versus prior simulators.