Position graph abstraction plus SHAPER/SHAW heuristics enable shuttling-aware compilation on trapped-ion machines, succeeding on extreme cases where baselines fail and yielding 1.45x average (up to 4x) speedups.
In 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA)
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Efficient Compilation for Shuttling Trapped-Ion Machines via the Position Graph Architectural Abstraction
Position graph abstraction plus SHAPER/SHAW heuristics enable shuttling-aware compilation on trapped-ion machines, succeeding on extreme cases where baselines fail and yielding 1.45x average (up to 4x) speedups.