Pith. sign in

EvoDRC: A Self-Evolving Agentic Framework for Automated DRC Violation Repair

1 Pith paper cite this work. Polarity classification is still indexing.

1 Pith paper citing it
abstract

Design rule check (DRC) closure remains a major bottleneck in advanced-node physical design. Although detailed routers are rule-aware, residual design rule violations (DRVs) often require manual engineering change order iterations. Automating this process is challenging because repairs must account for complex geometric interactions, preserve circuit connectivity, and avoid introducing new violations. We present EvoDRC, a skill-evolution framework for agentic block-level DRC repair. EvoDRC initializes layer-specific repair skills using knowledge distilled from an unrelated reference design and continuously evolves these skills using traceable repair experience collected from the target design. EvoDRC decomposes the layout into bounded repair regions and assigns an LLM repair agent to each region. Local DRC analysis, connectivity-checking, and impact-preview tools provide feedback on proposed modifications. Repair operations and their resulting DRV changes are stored in a knowledge database and used to evolve the repair skills. Experiments on seven block-level designs from the DAC26 DRC Benchmark show that EvoDRC achieves a 73.5\% overall reduction compared to the reported baseline.

fields

cs.AI 1

years

2026 1

verdicts

CONDITIONAL 1

representative citing papers

AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuits

cs.AI · 2026-08-04 · conditional · novelty 6.0

An agentic framework with a minimal-disturbance router and independent verifier clears post-route hybrid-bond spacing defects in 3D-IC designs (7/9 on one backbone, 9/9 on another) with low disturbance and zero clock-net changes.

citing papers explorer

Showing 1 of 1 citing paper.

  • AgenticECO: An Agentic Framework for ECO on 3D Integrated Circuits cs.AI · 2026-08-04 · conditional · none · ref 17 · internal anchor

    An agentic framework with a minimal-disturbance router and independent verifier clears post-route hybrid-bond spacing defects in 3D-IC designs (7/9 on one backbone, 9/9 on another) with low disturbance and zero clock-net changes.