EULER-ADAS is a SIMD-unified logarithmic-posit engine supporting Posit-(8,0), (16,1), and (32,2) that reduces LUTs by up to 41%, power by up to 72%, and energy-delay product by up to 10x versus prior Posit designs while staying within 1.5% of FP32 accuracy on ADAS workloads.
Dedicated FPGA Implementation of the Gaussian TinyYOLOv3 Accelerator,
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TREA is a low-precision time-multiplexed edge accelerator using dual-precision SIMD MAC units, structured pruning, and reconfigurable activation cores to deliver up to 9x kernel-level latency reduction for object detection and classification.
citing papers explorer
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EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration
EULER-ADAS is a SIMD-unified logarithmic-posit engine supporting Posit-(8,0), (16,1), and (32,2) that reduces LUTs by up to 41%, power by up to 72%, and energy-delay product by up to 10x versus prior Posit designs while staying within 1.5% of FP32 accuracy on ADAS workloads.
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TREA: Low-precision Time-Multiplexed, Resource-Efficient Edge Accelerator for Object Detection and Classification
TREA is a low-precision time-multiplexed edge accelerator using dual-precision SIMD MAC units, structured pruning, and reconfigurable activation cores to deliver up to 9x kernel-level latency reduction for object detection and classification.