A time-domain popcount built from programmable delay lines and arbiters is demonstrated on FPGA, giving asynchronous Tsetlin Machine inference reported latency, power, and resource savings over adder-based designs.
FPGA optimized architecture of XNOR-POPCOUNT,
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Efficient FPGA Implementation of Time-Domain Popcount for Low-Complexity Machine Learning
A time-domain popcount built from programmable delay lines and arbiters is demonstrated on FPGA, giving asynchronous Tsetlin Machine inference reported latency, power, and resource savings over adder-based designs.