A full-stack LUT-as-neuron FPGA framework reports up to 205× lower latency than BNN accelerators and higher LUT efficiency than prior differentiable LUT networks at competitive binary accuracy.
Leo: Online {ML-based}traffic classification at{Multi-Terabit}line rate,
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.AR 1years
2026 1verdicts
CONDITIONAL 1representative citing papers
citing papers explorer
-
FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs
A full-stack LUT-as-neuron FPGA framework reports up to 205× lower latency than BNN accelerators and higher LUT efficiency than prior differentiable LUT networks at competitive binary accuracy.