The paper presents circuit designs and simulation results for asynchronously resettable RSFQ gates (AND, OR, XOR, inverter) and memory cells (DFF, TFF, multi-flux DRO) built around the bidirectional alpha cell.
A layout design flow for rsfq circuits based on cell clustering and mixed wiring of jtls and ptls,
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AR-SFQ: Asynchronous Reset Library Using {\alpha}-Cell Design
The paper presents circuit designs and simulation results for asynchronously resettable RSFQ gates (AND, OR, XOR, inverter) and memory cells (DFF, TFF, multi-flux DRO) built around the bidirectional alpha cell.