A full-stack LUT-as-neuron FPGA framework reports up to 205× lower latency than BNN accelerators and higher LUT efficiency than prior differentiable LUT networks at competitive binary accuracy.
Bi-real net: Enhancing the performance of 1-bit cnns with improved representational capability and advanced training algorithm,
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FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs
A full-stack LUT-as-neuron FPGA framework reports up to 205× lower latency than BNN accelerators and higher LUT efficiency than prior differentiable LUT networks at competitive binary accuracy.