A hybrid ASIC+eFPGA architecture is proposed to add adaptive security mechanisms to edge LLM inference while retaining ASIC efficiency.
One flip away from chaos: Unraveling single points of failure in quantized dnn s,
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Secure eFPGA-Enabled Edge LLM Inference: Architectural and Hardware Countermeasures
A hybrid ASIC+eFPGA architecture is proposed to add adaptive security mechanisms to edge LLM inference while retaining ASIC efficiency.