AraXL scales a RISC-V vector processor to 64 lanes and 64 Kibit vector registers by replacing all-to-all interconnects with pipelined hierarchical and ring links, reaching 146 GFLOPs and 40.1 GFLOPs/W in 22nm simulation.
A RISC-V Simulator and Benchmark Suite for Designing and Evaluating Vector Architectures,
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AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors
AraXL scales a RISC-V vector processor to 64 lanes and 64 Kibit vector registers by replacing all-to-all interconnects with pipelined hierarchical and ring links, reaching 146 GFLOPs and 40.1 GFLOPs/W in 22nm simulation.