A new dataset of VHDL, Chisel, and PyMTL3 code paired with compiled Verilog improves LLM Verilog generation by up to 23% on VerilogEvalV2 after fine-tuning.
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hdl2v: A Code Translation Dataset for Enhanced LLM Verilog Generation
A new dataset of VHDL, Chisel, and PyMTL3 code paired with compiled Verilog improves LLM Verilog generation by up to 23% on VerilogEvalV2 after fine-tuning.