17 nm SiO2 oxide thickness minimizes threshold voltage variability below 63 mV standard deviation in dense 7x7 silicon quantum dot arrays fabricated via 300 mm CMOS and EUV lithography.
Elsayed et al., Low charge noise quantum dots with industrial CMOS manufacturing, Npj Quantum Inf 10, 70 (2024)
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
quant-ph 1years
2026 1verdicts
UNVERDICTED 1representative citing papers
citing papers explorer
-
Understanding oxide-thickness-dependent variability in dense Si-MOS quantum dot arrays
17 nm SiO2 oxide thickness minimizes threshold voltage variability below 63 mV standard deviation in dense 7x7 silicon quantum dot arrays fabricated via 300 mm CMOS and EUV lithography.