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Proceedings of the 50th Annual International Symposium on Computer Architecture , articleno =

3 Pith papers cite this work. Polarity classification is still indexing.

3 Pith papers citing it

fields

cs.CR 2 cs.AR 1

years

2026 2 2025 1

representative citing papers

Enabling AI ASICs for Zero Knowledge Proof

cs.AR · 2026-04-20 · conditional · novelty 8.0

MORPH reformulates ZKP MSM and NTT kernels into GEMM operations for TPUs using a new Big-T complexity model, achieving up to 10x NTT throughput over GZKP.

Leveraging ASIC AI Chips for Homomorphic Encryption

cs.CR · 2025-01-13 · accept · novelty 7.0

CROSS compiler maps HE workloads to TPU architecture via basis-aligned and memory-aligned transformations, reporting higher throughput-per-watt than prior GPU and ASIC libraries on NTT and HE operators.

citing papers explorer

Showing 3 of 3 citing papers.

  • Enabling AI ASICs for Zero Knowledge Proof cs.AR · 2026-04-20 · conditional · none · ref 23

    MORPH reformulates ZKP MSM and NTT kernels into GEMM operations for TPUs using a new Big-T complexity model, achieving up to 10x NTT throughput over GZKP.

  • Privatar: Scalable Privacy-preserving Multi-user VR via Secure Offloading cs.CR · 2026-04-19 · unverdicted · none · ref 204

    Privatar uses horizontal frequency partitioning and distribution-aware minimal perturbation to enable private offloading of VR avatar reconstruction, supporting 2.37x more users with modest overhead.

  • Leveraging ASIC AI Chips for Homomorphic Encryption cs.CR · 2025-01-13 · accept · none · ref 41

    CROSS compiler maps HE workloads to TPU architecture via basis-aligned and memory-aligned transformations, reporting higher throughput-per-watt than prior GPU and ASIC libraries on NTT and HE operators.