The authors design parallel iterative NTT/INTT accelerators for PQC using unified redundant arithmetic, integrated scaling, and hierarchical Montgomery multipliers, claiming higher clock frequencies and reduced execution times on FPGA with competitive resources.
Cohen, A Course in Computational Algebraic Number Theory, Springer-Verlag, New York, 1993
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High-Performance NTT Accelerators for PQC leveraging Unified Redundant Arithmetic and Fine-Tuned Microarchitecture
The authors design parallel iterative NTT/INTT accelerators for PQC using unified redundant arithmetic, integrated scaling, and hierarchical Montgomery multipliers, claiming higher clock frequencies and reduced execution times on FPGA with competitive resources.