SAGA reduces AI agent task completion time by 1.64x on 64-GPU clusters by scheduling at the full workflow level with execution graphs, affinity batching, and completion-time fairness.
Designing a QEMU plugin to profile multicore long vector RISC-V architectures: RAVE
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uLEAD-TabPFN detects anomalies in tabular data by scoring violations of conditional dependencies estimated via frozen PFNs with uncertainty awareness, achieving top average rank and up to 20% ROC-AUC gains on high-dimensional ADBench datasets.
A systematic mapping study of 87 papers derives an architecture-based taxonomy for Workflow as a Service brokers and identifies future research directions.
Three scheduling strategies for hybrid quantum-HPC systems cut classical resource use by up to 64% or boost QPU utilization depending on workload balance, validated on real hardware.
The EPAC chip integrates three RISC-V tiles connected by a CHI network-on-chip and has been successfully taped out and validated in GF22FDX technology as part of the European Processor Initiative.
citing papers explorer
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SAGA: Workflow-Atomic Scheduling for AI Agent Inference on GPU Clusters
SAGA reduces AI agent task completion time by 1.64x on 64-GPU clusters by scheduling at the full workflow level with execution graphs, affinity batching, and completion-time fairness.
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uLEAD-TabPFN: Uncertainty-aware Dependency-based Anomaly Detection with TabPFN
uLEAD-TabPFN detects anomalies in tabular data by scoring violations of conditional dependencies estimated via frozen PFNs with uncertainty awareness, achieving top average rank and up to 20% ROC-AUC gains on high-dimensional ADBench datasets.
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Workflow as a Service Broker in Cloud Environment: A Systematic Mapping Study
A systematic mapping study of 87 papers derives an architecture-based taxonomy for Workflow as a Service brokers and identifies future research directions.
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Three ways to share a QPU: Scheduling strategies for hybrid Quantum-HPC applications
Three scheduling strategies for hybrid quantum-HPC systems cut classical resource use by up to 64% or boost QPU utilization depending on workload balance, validated on real hardware.
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EPAC: The Last Dance
The EPAC chip integrates three RISC-V tiles connected by a CHI network-on-chip and has been successfully taped out and validated in GF22FDX technology as part of the European Processor Initiative.