PLoRA places LoRA adapters and KV cache in CXL pooled memory with near-data processors, cutting decode latency by about 6.6x versus S-LoRA in simulation.
Compute express link (CXL) 3.1 specification,
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PLoRA: An NDP-Enhanced Pooled-Memory System for Cost-Efficient Multi-LoRA Serving
PLoRA places LoRA adapters and KV cache in CXL pooled memory with near-data processors, cutting decode latency by about 6.6x versus S-LoRA in simulation.