A multi-level MLIR/xDSL backend for the Snitch RISC-V accelerator reaches up to 95% FPU utilization on micro-kernels and 90% when lowered from linalg, without register spilling.
High Performance Code Generation in MLIR: An Early Case Study with GEMM
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abstract
This article is primarily meant to present an early case study on using MLIR, a new compiler intermediate representation infrastructure, for high-performance code generation. Aspects of MLIR covered in particular include memrefs, the affine dialect, and polyhedral utilities and pass infrastructure surrounding those. This article is also aimed at showing the role compiler infrastructure could play in generating code that is competitive with highly tuned manually developed libraries, albeit in a more modular, reusable, and automatable way.
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A Multi-level Compiler Backend for Accelerated Micro-kernels Targeting RISC-V ISA Extensions
A multi-level MLIR/xDSL backend for the Snitch RISC-V accelerator reaches up to 95% FPU utilization on micro-kernels and 90% when lowered from linalg, without register spilling.