Jointly optimizing chiplet placement and inter-chiplet topology reduces ICI latency by up to 62% for cache-coherent traffic versus a 2D mesh baseline.
Chiplet placement for 2.5 d ic with sequence pair based tree and thermal consideration,
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PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies
Jointly optimizing chiplet placement and inter-chiplet topology reduces ICI latency by up to 62% for cache-coherent traffic versus a 2D mesh baseline.