Fusing an ASIC mapper with a reinforcement-learning-chosen partial cell library improves FPGA LUT count and area-delay product by about 9% on average.
Technology mapping for fpgas with embedded memory blocks
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Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper
Fusing an ASIC mapper with a reinforcement-learning-chosen partial cell library improves FPGA LUT count and area-delay product by about 9% on average.