Multi-agent LLMs automate testbench creation to produce efficient fine-tuning data, enabling a model to match state-of-the-art performance on specification-to-Verilog generation with less training data on the VerilogEval v2 benchmark.
Automated test case generation for digital system designs: A mapping study on vhdl, verilog, and systemverilog description languages,
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Exploring LLM-based Verilog Code Generation with Data-Efficient Fine-Tuning and Testbench Automation
Multi-agent LLMs automate testbench creation to produce efficient fine-tuning data, enabling a model to match state-of-the-art performance on specification-to-Verilog generation with less training data on the VerilogEval v2 benchmark.