A Rocq formalization of RISC-V using Interaction Trees provides machine-checked instruction semantics, an executable simulator, and cross-level verification case studies connecting LLVM IR to hardware.
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Interaction Tree Semantics for RISC-V: Bridging Compiler and Hardware Verification
A Rocq formalization of RISC-V using Interaction Trees provides machine-checked instruction semantics, an executable simulator, and cross-level verification case studies connecting LLVM IR to hardware.