COMPOSE is a timing-driven composable CGRA architecture that fuses cross-iteration operations and defers registration to deliver 1.6x performance and 2.9x EDP gains over prior CGRA designs for recurrence-bound loops.
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4 Pith papers cite this work, alongside 7 external citations. Polarity classification is still indexing.
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Proposes embedding transaction monitors and coherence checkers in a trusted silicon interposer to secure 2.5D chiplet systems against interconnect, coherence, and side-channel attacks without modifying untrusted chiplets.
Aurora reached 1.01 EF/s FP64 HPL and 11.64 EF/s HPL-MxP through locality-aware mapping, CPU-GPU pipelining, mixed-precision orchestration, and hybrid resilience on a large Intel GPU-based system.
A survey categorizing vendor mechanisms and user-level libraries for GPU-centric communication within and across nodes, with discussion of benefits, challenges, and open questions.
citing papers explorer
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COMPOSE: Static Timing-driven Composable Reconfigurable Architecture for Accelerating Recurrence-Bound Loops
COMPOSE is a timing-driven composable CGRA architecture that fuses cross-iteration operations and defers registration to deliver 1.6x performance and 2.9x EDP gains over prior CGRA designs for recurrence-bound loops.
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2.5D Root of Trust: Securing the Chiplet Ecosystem
Proposes embedding transaction monitors and coherence checkers in a trusted silicon interposer to secure 2.5D chiplet systems against interconnect, coherence, and side-channel attacks without modifying untrusted chiplets.
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Sustaining Exascale Performance: Lessons from HPL and HPL-MxP on Aurora
Aurora reached 1.01 EF/s FP64 HPL and 11.64 EF/s HPL-MxP through locality-aware mapping, CPU-GPU pipelining, mixed-precision orchestration, and hybrid resilience on a large Intel GPU-based system.
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The Landscape of GPU-Centric Communication
A survey categorizing vendor mechanisms and user-level libraries for GPU-centric communication within and across nodes, with discussion of benefits, challenges, and open questions.