A binary vector encoding with truth-table spin interactions gives probabilistic Ising machines competitive graph-coloring accuracy and a 1024-neuron FPGA implementation with large speedups.
InProceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA ’24, 43 (Association for Computing Machinery, New York, NY , USA, 2024)
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.AR 1years
2025 1verdicts
CONDITIONAL 1representative citing papers
citing papers explorer
-
Efficient Optimization Accelerator Framework for Multistate Ising Problems
A binary vector encoding with truth-table spin interactions gives probabilistic Ising machines competitive graph-coloring accuracy and a 1024-neuron FPGA implementation with large speedups.