A RISC-V instruction-set extension with a weight-embedded lookahead counter and a variable-cycle MAC unit accelerates sparse DNN inference on FPGAs by up to 5x at modest resource cost.
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Hardware/Software Co-Design of RISC-V Extensions for Accelerating Sparse DNNs on FPGAs
A RISC-V instruction-set extension with a weight-embedded lookahead counter and a variable-cycle MAC unit accelerates sparse DNN inference on FPGAs by up to 5x at modest resource cost.