A fully pipelined ASIC implementation of step-length line segment detection processes one pixel per clock cycle, achieving 325 FPS at VGA and 25.54 mW at 100 MHz in 45nm.
Memory efficient ASIC implemen- tation of line hough transform,
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A Low-Latency ASIC Architecture for Real-Time Line Segment Detection
A fully pipelined ASIC implementation of step-length line segment detection processes one pixel per clock cycle, achieving 325 FPS at VGA and 25.54 mW at 100 MHz in 45nm.