TRAM achieves up to 27% power reduction in multipliers for CNNs and vision transformers by jointly training model weights and approximate multiplier designs.
Approximate logic synthesis using Boolean matrix factorization.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 41(1):15–28
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TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
TRAM achieves up to 27% power reduction in multipliers for CNNs and vision transformers by jointly training model weights and approximate multiplier designs.