An automatic RTL compiler generates a Stratix 10 FPGA accelerator that performs forward pass, backward pass, and weight update for CIFAR-10 CNNs in 16-bit fixed point, reporting up to 479 GOPS.
A framework for generat- ing high throughput CNN implementations on FPGAs,
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Automatic Compiler Based FPGA Accelerator for CNN Training
An automatic RTL compiler generates a Stratix 10 FPGA accelerator that performs forward pass, backward pass, and weight update for CIFAR-10 CNNs in 16-bit fixed point, reporting up to 479 GOPS.