Hardware-faithful verification with a HAL descriptor eliminates all 54 false 16-bit overflow alarms on 123 real IEC 61131-3 programs while preserving robustness proofs.
Springer Nature Switzerland, Moffett Field, CA, USA, 2024
2 Pith papers cite this work, alongside 3 external citations. Polarity classification is still indexing.
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cs.PL 2years
2026 2representative citing papers
ESBMC-PLC+ unifies support for all major IEC 61131-3 formats (ST, LD, SCL) in a single ESBMC backend with k-induction for unbounded safety proofs and extended function block semantics.
citing papers explorer
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ESBMC-Arduino: Closing the Deployment Gap for Formal Verification of Open-Hardware PLCs
Hardware-faithful verification with a HAL descriptor eliminates all 54 false 16-bit overflow alarms on 123 real IEC 61131-3 programs while preserving robustness proofs.
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ESBMC-PLC+: A Unified IEC 61131-3 Formal Verification Framework as a PLCverif Successor
ESBMC-PLC+ unifies support for all major IEC 61131-3 formats (ST, LD, SCL) in a single ESBMC backend with k-induction for unbounded safety proofs and extended function block semantics.