Integrating RVV tensor intrinsics into TVM's MetaSchedule autotuner yields AI kernels that are 29-50% faster than hand-written muRISCV-NN and 35-46% faster than compiler autovectorization on tested RVV 1.0 hardware.
Xuantie-910: A commercial multi-core 12-stage pipeline out-of-order 64-bit high performance risc-v processor with vector extension : Indus- trial product,
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Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs
Integrating RVV tensor intrinsics into TVM's MetaSchedule autotuner yields AI kernels that are 29-50% faster than hand-written muRISCV-NN and 35-46% faster than compiler autovectorization on tested RVV 1.0 hardware.