A 3D SRAM-eDRAM hybrid CIM design in 22nm FDSOI enables general-purpose matrix computations beyond dot products with claimed balance of latency, energy, and density.
A compute-in-memory hardware accelerator design with back-end-of-line (beol) transistor based reconfigurable interconnect,
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GEM3D CIM General Purpose Matrix Computation Using 3D Integrated SRAM eDRAM Hybrid Compute In Memory on Memory Architecture
A 3D SRAM-eDRAM hybrid CIM design in 22nm FDSOI enables general-purpose matrix computations beyond dot products with claimed balance of latency, energy, and density.