A customized RAG pipeline plus prompt-guided fine-tuning increases the number of functionally correct SystemVerilog assertions generated by LLMs, with a new 229-assertion benchmark.
Ieee standard for systemverilog–unified hardware design, specification, and verification language,
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
citation-role summary
background 1
citation-polarity summary
fields
cs.CL 1years
2025 1verdicts
CONDITIONAL 1roles
background 1polarities
support 1representative citing papers
citing papers explorer
-
Hybrid-NL2SVA: Integrating RAG and Finetuning for LLM-based NL2SVA
A customized RAG pipeline plus prompt-guided fine-tuning increases the number of functionally correct SystemVerilog assertions generated by LLMs, with a new 229-assertion benchmark.