A high-level fault model with bit-wise data constraints generates SBST programs for RISC execute units that reach 99.02 percent gate-level SAF coverage on MiniMIPS, outperforming a commercial ATPG's 97.73 percent in the reported experiment.
Software based self-testing of embedded processors
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High-Level Combined Deterministic and Pseudoexhuastive Test Generation for RISC Processors
A high-level fault model with bit-wise data constraints generates SBST programs for RISC execute units that reach 99.02 percent gate-level SAF coverage on MiniMIPS, outperforming a commercial ATPG's 97.73 percent in the reported experiment.