Enhancements to VTR enable modeling of multi-die FPGA routing, showing 3D FPGAs achieve up to 14% wirelength reduction and 6% CPD improvement over 2D while remaining routable.
Field-programmable gate array ar- chitecture for deep learning: Survey and future directions,
2 Pith papers cite this work. Polarity classification is still indexing.
2
Pith papers citing it
fields
cs.AR 2years
2026 2representative citing papers
A full-stack LUT-as-neuron FPGA framework reports up to 205× lower latency than BNN accelerators and higher LUT efficiency than prior differentiable LUT networks at competitive binary accuracy.
citing papers explorer
-
Modeling, Optimizing and Exploring Multi-Die FPGA Routing Architectures
Enhancements to VTR enable modeling of multi-die FPGA routing, showing 3D FPGAs achieve up to 14% wirelength reduction and 6% CPD improvement over 2D while remaining routable.
-
FPGN: Redefining Ultra-Fast Programmable Gate-based Neural Acceleration with Differentiable LUTs
A full-stack LUT-as-neuron FPGA framework reports up to 205× lower latency than BNN accelerators and higher LUT efficiency than prior differentiable LUT networks at competitive binary accuracy.