Two new heuristics reduce hardware-limited depth of commuting PPR groups by 10-20% on average (up to 50%) in QASMBench circuits compiled to PPRs.
Cyclone: Designing Efficient and Highly Parallel QCCD Architectural Codesigns for Fault Tolerant Quantum Memory
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Optimizing Parallel Execution of Commuting Pauli Product Rotations
Two new heuristics reduce hardware-limited depth of commuting PPR groups by 10-20% on average (up to 50%) in QASMBench circuits compiled to PPRs.